P-03 / FPGA & Digital Logic

FPGA Traffic-Light Intersection Controller

Built a finite-state traffic controller in Verilog, encoded safety in output logic, and validated the design through simulation and DE10-Lite LED hardware.

CompletedDocumented evidenceRecruiter summaryVerilogFinite-state machinesTerasic DE10-LiteQuartusLED hardware

Organization: Independent academic hardware project
Engineering problem: Sequence a two-direction intersection in hardware while making conflicting green outputs structurally impossible.
My role: Designed the control logic in Verilog, mapped outputs to physical LEDs, and validated behavior in simulation and on a Terasic DE10-Lite FPGA.
Verified result: Implemented mutually exclusive traffic phases and checked the sequence through simulation and physical output behavior.

INTERACTIVE / ARCHITECTURE

Trace the system.

N-01FPGA clock

Source clock for synchronous logic.

N-02Time base

Reduces the clock to observable phase events.

N-03Traffic FSM

Selects one legal traffic phase.

N-04Output decode

Drives paired red, yellow, and green indications.

N-05Physical LEDs

Makes logic state observable on hardware.

Note — Functional view; exact module names and divider constants are intentionally omitted until HDL is published.

MORE DETAIL AVAILABLE / ENGINEERING VIEW

Open the technical investigation.

Trace the project’s physics or control logic, subsystem interactions, failure modes, and evidence boundaries.

Project Overview

This project implements a traffic-light controller as synchronous digital hardware on a Terasic DE10-Lite FPGA. The central concern is not visual sequencing alone: the logic must never command conflicting green signals.

My Role

Designed the Verilog control logic, organized the state and transition behavior, mapped signals to LEDs, and checked the design through simulation and on-hardware observation.

Testing and Validation

Simulation was used to inspect state order and output combinations. On-hardware validation then checked reset behavior, visible sequencing, and the absence of conflicting green indications.

Results

The design implemented a mutually exclusive two-direction sequence and exposed the logic on physical LEDs. Exact timing values and waveform measurements are not published until the source and test artifacts are added.

What I Learned

The project made safety constraints concrete: a well-structured state machine limits what the hardware can command, while simulation and physical outputs reveal different classes of error.

Media and Documentation

The case study is ready for an RTL diagram, simulation waveform, annotated pin map, and a clear photograph of the DE10-Lite and breadboard intersection.

Next case studyUltrasonic Sensor and Servo PCB