Problem
Sequence a two-direction intersection in hardware while making conflicting green outputs structurally impossible.
P-03 / FPGA & Digital Logic
FPGA Traffic-Light Intersection Controller
Built a finite-state traffic controller in Verilog, encoded safety in output logic, and validated the design through simulation and DE10-Lite LED hardware.
- Organization
- Independent academic hardware project
- Engineering problem
- Sequence a two-direction intersection in hardware while making conflicting green outputs structurally impossible.
- My role
- Designed the control logic in Verilog, mapped outputs to physical LEDs, and validated behavior in simulation and on a Terasic DE10-Lite FPGA.
- Verified result
- Implemented mutually exclusive traffic phases and checked the sequence through simulation and physical output behavior.
RECRUITER VIEW / SIX-POINT SUMMARY
The project in under a minute.
Ownership, evidence, and relevance are kept visible. The deeper implementation layer is one switch away.
My role
Designed the control logic in Verilog, mapped outputs to physical LEDs, and validated behavior in simulation and on a Terasic DE10-Lite FPGA.
What I contributed
Built a finite-state traffic controller in Verilog, encoded safety in output logic, and validated the design through simulation and DE10-Lite LED hardware.
Technologies
Verilog · Finite-state machines · Terasic DE10-Lite · Quartus · LED hardware
Validation / result
Implemented mutually exclusive traffic phases and checked the sequence through simulation and physical output behavior.
Lesson / relevance
The project made safety constraints concrete: a well-structured state machine limits what the hardware can command, while simulation and physical outputs reveal different classes of error.