The problem
Sequence a two-direction intersection in hardware while making conflicting green outputs structurally impossible.
P-04 / FPGA & Digital Logic
FPGA Traffic-Light Intersection Controller
Built a finite-state traffic controller in Verilog, encoded safety in output logic, and validated the design through simulation and DE10-Lite LED hardware.
Result / current evidenceImplemented mutually exclusive traffic phases and checked the sequence through simulation and physical output behavior.
PROJECT VIEW
Overview
The fast path is selected.
OVERVIEW / THE SIGNAL
Three things that matter.
Verilog · Finite-state machines · Terasic DE10-Lite · Quartus · LED hardware
What I owned
Designed the control logic in Verilog, mapped outputs to physical LEDs, and validated behavior in simulation and on a Terasic DE10-Lite FPGA.
The evidence
Implemented mutually exclusive traffic phases and checked the sequence through simulation and physical output behavior.